The present invention relates to a clock signal generating apparatus for use in a system where a video signal is digitally processed.
There are known video tape recorders (VTRs) each furnished with a digitized video signal processing circuit, such as the one disclosed in "Electronics Life", July 1988, pp. 47-53.
FIG. 11 is a block diagram showing an exemplary configuration of a reproduced video signal processing circuit employed in one conventional VTR of the type mentioned. In this diagram, a composite signal, which is obtained by mixing a low-frequency converted C signal with an FM-Y signal reproduced from a magnetic tape (not shown) by a reproducing head 1, is amplified by a head amplifier 2. Subsequently the FM-Y signal is separated by a high pass filter 3 and then is supplied to an A-D converter 4. Meanwhile the low-frequency converted C signal is separated by a low pass filter (not shown) and then is supplied to a reproduced color signal processing circuit (not shown). Since the present invention is not concerned directly with the C signal processing system, no description will be given below with regard to the color signal processing circuit. The FM-Y signal inputted to the A-D converter 4 is digitized therein and is supplied to an FM demodulator 5, where the digitized FM-Y signal is demodulated to become a digital Y signal. This Y signal is deemphasized by a next deemphasis circuit 6 in the next stage, and the Y signal thus processed is supplied to a sharpness circuit 7 where the sharpness thereof is adjusted. And after correction of the time base in a TBC 8, its output is supplied to a D-A converter (not shown) where the Y signal is converted into an analog signal.
In the Y signal reproducing system thus constituted, the A-D converter 4 and the FM demodulator 5 use a clock signal whose frequency is double that of a system clock signal having a 910-fold higher frequency (hereinafter referred to as 910fH) in comparison with a horizontal sync signal. Meanwhile the sharpness circuit 7 and the TBC 8 use the system clock signal of the frequency 910fH. This system clock signal is generated by first converting the output of the deemphasis circuit 6 into an analog Y signal by the D-A converter 9, then separating a horizontal sync signal from the analog Y signal by a horizontal sync separator 10, and supplying the horizontal sync signal to a PLL circuit 11. The PLL circuit 11 comprises a phase comparator 12 for comparing the phase of the horizontal sync signal with that of an internal comparison signal, a low pass filter 13, a VCO 14 for generating a system clock signal of the frequency 910fH, a 1/910 counter 15 which counts the output of the VCO 14 and is reset upon arrival of the counted value at 910, and a comparison signal generator 16 for generating a comparison signal of rectangular or similar waves from the counted value of the 1/910 counter 15 and supplying the comparison signal to the phase comparator 12.
However, in the conventional VTR mentioned above, there exists a disadvantage that an additional D-A converter is required for once converting the digitized Y signal into an analog signal to produce a clock signal used in the digital processing system.
Furthermore, due to occurrence of a great phase error resulting from some skew at a head switching time or variations of the horizontal sync signal period in the vertical blanking interval, there arises another problem that the operation is rendered unstable in an upper portion and so forth of the screen.